A switch mode power converter (also referred to as a “power converter”) is a power supply or power processing circuit that converts an input voltage waveform into a specified output voltage waveform. Controllers associated with power converters manage an operation thereof by controlling the conduction periods of switches employed therein. Generally, controllers are coupled between an input and output of the power converter in a feedback loop configuration (also referred to as a “control loop” or “closed control loop”).
Typically, the controller measures an output characteristic (e.g., an output voltage) of the power converter and based thereon modifies a duty cycle of the switches of the power converter. The duty cycle is a ratio represented by a conduction period of a switch to a switching period thereof. Thus, if a switch conducts for half of the switching period, the duty cycle for the switch would be 0.5 (or 50 percent). Additionally, as the needs for systems such as microprocessors powered by the power converter dynamically change (e.g., as a computational load on the microprocessor changes), the controller is typically configured to dynamically increase or decrease the duty cycle of the switches therein to maintain the output characteristic at a desired value.
As discussed above, power converters are frequently employed to power loads having tight regulation characteristics such as a microprocessor with, for instance, five volts provided from a source of electrical power (e.g., a voltage source). To provide the voltage conversion and regulation functions, the power converters include switches such as metal-oxide semiconductor field-effect transistors (“MOSFETs”) that are coupled to the voltage source and periodically switch a reactive circuit element such as an inductor to the voltage source at a switching frequency that may be on the order of a half megahertz (“MHz”) or higher. To maintain high power conversion efficiency and low cost, the switching frequency of the power converter is generally limited to a value dependent on characteristics of the switches.
As the performance of microprocessors continues to increase with continuing improvements in silicon technology, new demands are placed on the power converters that power the microprocessors. The power absorbed by a microprocessor, and generally any digital system implemented with complementary metal-oxide semiconductor (“CMOS”) technology, is substantially proportional to a clock frequency and to a square of an operating voltage thereof. Thus, new digital system designs including microprocessors are pressed to operate at a low supply voltage and low clock frequency in view of a digital workload that may vary dynamically over time.
A newer consideration associated with the use of power converters employed with digital systems is the need to quickly respond to step changes in the output current (also, the load current) when the digital system enters a halt or idle state or, alternatively, when the digital system resumes its normal high performance workload. For example, the output current absorbed by a high performance microprocessor can change as fast as 1000 amperes per microsecond (“A/μs”) with little or no tolerance to forego a tight output voltage regulation limit [such as ±200 millivolts (“mVs”) for a 1.5 volt output].
Another new demand is the need for the power converter to quickly and controllably change the regulated output voltage without voltage overshoots as the microprocessor responds to the dynamic changes in the digital workload. Reducing the supply voltage when the digital workload is reduced accommodates a reduction in microprocessor clock frequency, which proportionately reduces power dissipation. Ideally, the output voltage of the power converter is changed in a sufficiently controlled and predictable manner so that a clock of the microprocessor can continue to operate during the voltage transition. Changing output voltage for a dynamically changing microprocessor workload is referred to as dynamic voltage scaling (“DVS”), which is a technique that dramatically reduces energy consumption in high performance digital systems.
The power converter is thus an essential element for achieving a substantial reduction in energy consumption associated with digital systems. The power converter is measured by its response time to the changes, resulting in closely watched performance metrics for market acceptance. A power converter should continue to maintain tight output voltage regulation limits in response to normal changes in environmental conditions (e.g., input voltage and temperature variations), while producing a substantially dc output voltage with tightly specified ripple content such as ripple voltage, current or frequency. The power converter should also perform the power conversion tasks with little or no reduction in power conversion efficiency.
Analog linear controllers have traditionally been used to control an output characteristic of a power converter such as an output voltage. A recognized disadvantage of analog linear controllers is the limited dynamic response time. The bandwidth of an analog linear controller for a power converter, which exhibits an inverse relationship with the output voltage response time and the output current transition times, is typically limited to approximately one-fifth to one-tenth of a switching frequency of the power converter to achieve the necessary gain and phase margins for stability in the control loop. The power converters with higher switching frequencies can achieve faster response times and produce lower output ripple voltages, but often incur a reduction in power conversion efficiency and in physical density produced by increased switching losses in the semiconductor devices, by skin effect in various conductors, and by increased losses in magnetic cores of the magnetic devices therein. The optimal switching frequency from a perspective of a power converter response time is generally substantially higher than the optimal switching frequency from a perspective of power conversion efficiency. Thus, an optimum linear controller designed for a power converter with a switching frequency of 500 kilohertz (“kHz”) cannot achieve a two μs output voltage transition because the control system bandwidth is also 500 kHz, which is not practical with an approach using a linear controller.
Various design approaches to power converter design have been attempted to meet the difficult and interacting choices. One design approach uses sufficiently fast switches to achieve higher efficiency and small size with a switching frequency over five MHz. Theoretically, linear controllers can handle control bandwidths approaching one MHz. However, it is quite difficult to provide control robustness for the power converter because of noise, plant variations, parasitic influences, and non-ideal error amplifiers. Another design approach uses multiple interleaved power trains (which include switch(es) of the power converter) to produce a higher effective output ripple frequency that can be more easily filtered with a small output capacitor and that accommodates wider control bandwidth. Interleaved power trains generally allow the efficient use of smaller output filter components, particularly output inductors, which are necessary to achieve fast output voltage and current response times. Even if a high switching frequency and interleaved power trains are used, however, sufficient control bandwidth and response times are generally impractical with a linear controller.
To reduce the response time for the output of a power converter employing a buck topology to a desired state (particularly for step changes in the output voltage), Pontryagin's principle has been used to generate an ideal control signal to transition the output state of a power converter in minimum period of time. A control law and experimental results using this approach are described by A. Soto, et al. in “Analysis of the Buck Converter for Scaling the Supply Voltage of Digital Circuits,” published in the Proceedings of the IEEE Applied Power Electronics Conference, pp. 711-717, 2003, which is incorporated herein by reference. In the aforementioned reference, control of the conduction and non-conduction periods for the high frequency switches in the power converter with an intermediate switching transition is described that achieves a minimum response time.
Digital control approaches to power converters have also been introduced in the past. There are certain applications in which digital control is more advantageous than analog control, particularly in the ability to introduce nonlinear elements in the control process. The idea of introducing nonlinear control has also been explored by D. Goder, et al. (“Goder”), in “V2 Architecture Provides Ultra-Fast Transient Response in Switch Mode Power Supplies,” published in the Proceedings of HFPC Power Conversion, pp. 414-420, 1996, and by A. Barrado, et al., in “New DC-DC Converter with Low Output Voltage and Fast Transient Response,” published in the Proceedings of the IEEE Applied Power Electronics Conference, pp. 432-437, 2003, which are incorporated herein by reference. Nonlinear control is employed to provide a fast transient response for the power converter without relying on a linear high bandwidth control for large step changes in the output current or in step changes in the reference voltage for the output voltage set point. On the other hand, slower linear control combined with nonlinear control can provide accurate steady-state output voltage regulation for slower power converter perturbations such as input voltage variation, temperature drift, and component aging.
The use of digital control, particularly including linear and nonlinear control, has to address two main problems. First, the nonlinear response should accommodate, without interference, steady-state output voltage regulation with acceptable accuracy. Otherwise, the fast transient response will still be substantially affected by the slower linear loop. Second, the slower linear loop should not interfere with the nonlinear response in a way that leads to instabilities in an overall control of the power converter.
Well known nonlinear strategies such as V2 control as described by Goder or the use of hysteretic control methods have attempted to address these issues. A remaining problem, however, is the introduction of significant noise in the control loop as system bandwidth is increased. Both strategies sense the output ripple voltage, which is very small compared to its dc value. The output ripple voltage, which is generally a triangular waveform, is determined by the effective series resistance (“ESR”) of the output capacitors (or of an added resistor) and is generally present, as described by R. Redl, et al. (“Redl”), in “Optimizing the Load Transient Response of the Buck Converter,” published in the Proceedings of the IEEE Applied Power Electronics Conference, pp. 170-176, 1998, which is incorporated herein by reference. Sensing output ripple voltage often worsens output voltage regulation, particularly for step load changes. The transient response of the control loop for step changes in the output voltage becomes very aggressive since the controller attempts to correct the output voltage error in one switching action, which may be faster than a minimum time. The output inductor current does not settle at the end of a transient and the magnitude thereof should be limited during a voltage step to prevent inductor saturation.
Accordingly, what is needed in the art is a controller and method of operating a power converter that can provide fast response times to a step change in an output characteristic (e.g., output voltage) as well as maintain output voltage regulation with close tolerance during a step change in the output current. Tight control of the output voltage during steady-state operation should be maintained with limited response to noise in the control loop. Conventional controllers are substantially susceptible to noise when expanding a bandwidth of the control loop to a sufficient level to provide fast output voltage control without unnecessary voltage overshoot or control loop stability margins. A number of attempts have been made to meet the design objectives without avail.